How To Draw A Timing Diagram Flip Flop

(introduction...)

Titel: Flip-Flops

Objectives:

- Understand the Flip-Flop principle
- Know the three basic Flip-Flops (RS, D, JK)
- Able to analyze timing diagrams

Time	Method	Topic	Way	Remark
		* Review Lesson 6
		* Introduction
		* RS Flip-Flops
		* Clocked RS-FF
		* Timing diagram
		* D-FF
		* FF switching time
		* JK-FF
		* JK-MS-FF
		* Review exercise		Worksheet No. 7
	S: Speech D: Word Q/A: Question/Respond F: Exercise		B: Boardscript P: Motion-picture show Ex: Case HO: Hands-On WS: Worksheet HT: Hand-Out

Introduction

Flip-Flops

Sometimes in that location is a need of digital devices or circuits whose output volition remain unchanged, once set, even if there is a change in input.

RS Flip-Flops

A Flip-Flop is a bistable electronic circuit that has two stable states.

Þ Output is either 0 or 5V dc

The Flip-Flop tin can be regarded every bit a retentivity device. Information technology tin be used to store one binary digit at the output.

Fig. 7-ane: RS Flip-Flop, logic circuit and device symbol

HO: What is the truth table for the circuit above?

Solution:

Fig. 7-ii: Truth table, RS Flip-Flop

R	Southward	Q	Activeness
0	0	Last value	No modify
0	i	1	Set
ane	0	0	Reset
one	1	?	Forbidden

If both inputs (R, Due south) are high at once, the output can not be determined before; therefore, it is a forbidden land.

Ex: Create a RS Flip-Flop with NAND gates.

Fig. vii-3: RS Flip-Flop with NAND gates

Notation: The inputs (R, S) are indicated with an overbar so they are inverted.

Fig. 7-4: Logic symbol, RS Flip-Bomb with inverted inputs

Clocked RS Flip-Bomb

Fig. 7-5: Clocked RS Flip-Bomb

This Flip-Flop ca be enabled or disabled.

ENABLE ® low: R and S will have no upshot on the output

ENABLE ® high: R and S inputs volition be direct transmitted to the output

Fig. seven-6: Logic symbol, Clocked RS Flip-Flop

Timing diagram

A timing diagram is a drawing to make up one's mind the time dependent actions of logic devices.

Fig. vii-7: Timing diagram of a clocked RS Flip-Flop

Fig. 7-7 shows that the inputs (R, Southward) effect the output (Q) only when the clock bespeak (CLK) is high.

RS Flip-Flop application: Bounce gratuitous switch

D - Flip-Bomb (D-FF)

The generation of ii signals to drive a Flip-Flop is a disadvantage in many applications. This has led to the D-FF, a circuit that needs only a unmarried data input.

Fig. 7-8: D Flip-Flop, logic circuit and truth table

CLK ® depression: D can modify without upshot on the output

CLK ® high: Q is forced to equal the value of D

Ex: Create a four bit data memory with D-latches (D-FF).

Fig. 7-9: Data storage with D-FF

In Fig. 7-nine, when the clock goes loftier, input data is loaded into the Flip-Flops and appears at the output.

Suppose the data input is:

D₃D_iiD₁ D₀ = one 0 one 0

When the clock goes high this 4 bit discussion is loaded into the D-latches, resulting in an output of:

Q₃ Q_two Q₁ Q₀ = 1 0 i 0

Flip-Flop switching time

Fig. vii-ten: Timing diagram, FF switching fourth dimension

t_set:	Minimum of time that the date bit must be nowadays before the clock border hits (because of stray capacitance)
t_concord:	The data chip has to be hold long enough for the internal transistors to switch.
t_p:	Switching fourth dimension, diodes and transistors cannot switch states immediately. (some nanoseconds)

JK Flip-Flop (JK-FF)

Flip - Flops tin be used to build counters, JK-FF are the ideal elements for that purpose.

Fig. 7-11: JK-FF, logic circuit

Ex: What is the truth table for the circuit above?

Fig. seven-12: Truth table, JK-FF

CLK	J	Thousand	Q
X	0	0	last state
	0	ane	0
	1	0	i
	1	ane	toggle

J and One thousand ® low:	Both AND gates are disabled, clock pulses take no outcome. Q retains its concluding value.
J ® depression, K ® loftier:	The upper gate is disabled, just reset is possible (unless Q is already reset).
J ® high, K ® low:	The lower gate is disabled, just set is possible (unless Q is already high).
J and M ® high:	Set or reset is possible, the Flip-Bomb volition "toggle" on the next positive clock border. Toggle means to switch to the opposite state.

Fig. 7-thirteen: JK-FF's, logic symbols

Preset (PR) and Clear (CLR) are input signals to get a definite start point.

JK Principal-Slave FF (JK-MS-FF)

Fig. vii-fourteen: JK-MS-FF, logic circuit

Regardless what the primary does, the slave copies it. The slave copies the main on the negative clock edge. This circuit provides a way to avoid racing.

Fig. 7-15: JK-MS-FF, logic symbol

Available as TTL device: 74 LS 76

Source: http://www.nzdl.org/gsdlmod?e=d-00000-00---off-0cdl--00-0----0-10-0---0---0direct-10---4-------0-0l--11-en-50---20-help---00-0-1-00-0--4----0-0-11-10-0utfZz-8-00&cl=CL2.4&d=HASHfb0a7f85db79899f86b6a0.11.1.3>=1

Posted by: mahoneycattess.blogspot.com